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? 2011 microchip technology inc. ds80519d-page 1 pic18f66k80 the pic18f66k80 family devices that you have received conform functionally to the current device data sheet (ds39977 d ), except for the anomalies described in this document. the silicon issues discussed in the following pages are for silicon revisions with the device and revision ids listed in tab le 1 . the silicon issues are summarized in table 2 . the errata described in this document will be addressed in future revisions of the pic18f66k80 silicon. data sheet clarifications and corrections start on page 8 , following the discussion of silicon issues. the silicon revision level can be identified using the current version of mplab ? ide and microchip?s pro- grammers, debuggers and emulation tools, which are available at the microchip corporate web site ( www.microchip.com ). for example, to identify the silicon revision level using mplab ide in conjunction with mplab icd 3 or pickit? 3: 1. using the appropriate interface, connect the device to the mplab icd 3 programmer/ debugger or pickit? 3. 2. from the main menu in mplab ide, select configure>select device and then select the target part number in the dialog box. 3. select the mplab hardware tool ( debugger>select tool ). 4. perform a ?connect? operation to the device ( debugger>connect ). depending on the devel- opment tool used, the part number and device revision id value appear in the output window. the devrev values for the various pic18f66k80 silicon revisions are shown in ta b l e 1 . note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated in the last column of table 2 apply to the current silicon revision ( a4 ). note: if you are unable to extract the silicon revision level, please contact your local microchip sales office for assistance. table 1: silicon devrev values part number device id ( 1 ) revision id for silicon revision ( 2 ) a2 a3 a4 pic18f66k80 60e0 2h 3h 4h pic18f65k80 6140 pic18f46k80 6100 pic18f45k80 6160 pic18f26k80 6120 pic18f25k80 6180 pic18lf66k80 61c0 pic18lf65k80 6220 pic18lf46k80 61e0 pic18lf45k80 6240 pic18lf26k80 6200 pic18lf25k80 6260 note 1: the device ids (devid and devrev) are located at the last two implemented addresses of configuration memory space. they are shown in hex adecimal in the format, ?devid devrev?. 2: refer to the ?pic18f66k80 flash programming specification? (ds39972) for detailed information on device and revision ids for your specific device. pic18f66k80 family silicon errata and data sheet clarification
pic18f66k80 ds80519d-page 2 ? 2011 microchip technology inc. table 2: silicon issue summary module feature item number issue summary affected revisions ( 1 ) a2 a3 a4 analog-to-digital converter (a/d) a/d performance 1. the 12-bit a/d performance is outside of data sheet?s a/d converter specifications. xxx eusart synchronous transmit 2. when using the synchronous transmit mode, transmitted data may become cor- rupted if using the txxif bit to determine when to load the txregx register. x eccp auto-shutdown 3. the tri-state setting of the auto-shutdown feature in the enhanced pwm will not successfully drive the pin to tri-state. xxx ecan can clock source selection 4. clksel bit in the ciocon register is modifiable while the ecan module is active. x ultra low-power sleep sleep entry 5. entering ultra low-power sleep mode by setting reten = 0 and sreten = 1 , will cause the part to not be programmable through icsp?. x i pd and i dd maximum limit 6. maximum current limits may be higher than specified in table 31-2 of the data sheet. x reset (bor) enable/disable 7. an unexpected reset may occur if the brown-out reset module (bor) is dis- abled, and then re-enabled, when the high/low-voltage detection module (hlvd) is not enabled (hlvdcon<4> = 0 ). xxx ecan ewin 8. the enhanced window address feature, ewin<4:0>, in the ecancon register, will not move the bncon 0< n< 5 registers into the access window of ram. x mclre master clear enable 9. the master clear pin will not be readable when mclre is set to off for all 28-pin part variants (pic18f2xk80). xxx timer1/ timer3 gated enable 10. timer1 and timer3 gate control will not function up to the speed of f osc when the txcon is set to the system clock (txcon<7:6> = 01 ). xx note 1: only those issues indicated in the last column apply to the current silicon revision.
? 2011 microchip technology inc. ds80519d-page 3 pic18f66k80 silicon errata issues 1. module: analog-to-digital converter (a/d) the 12-bit a/d performance is outside of the data sheet?s a/d converter specifications. when used as a 12-bit a/d, the possible issues are high offset error, up to a maximum of 25 lsbs; high dnl error, up to a maximum of +6.0/-4.0 lsbs; and multiple missing codes, up to a maximum of twenty. users should evaluate the 12-bit a/d performance in their application using the suggested work around below. see table 3 for guidance specifications. the 12-bit a/d issues will be fixed in future revisions of this part. reduced bit resolution specifications can be derived by dividing, as appropriate. for instance, 10-bit guidance is obtained by dividing the parameters in ta bl e 3 by four. a/d o ffset the a/d may have high offset error, up to a maximum of 25 lsbs; it can be used if the a/d is calibrated for the offset. work around calibrate for offset in single-ended mode by connecting a/d +ve input to ground and taking the a/d reading. this will be the offset of the device and can be used to compensate for the subsequent a/d readings on the actual inputs. table 3: a/d converter characteristics affected silicon revisions note: this document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. only the issues indicated by the shaded column in the following tables apply to the current silicon revision ( a4 ). param no. sym characteristic min typ max units conditions a01 n r resolution ? ? 12 bit ? v ref ? 5.0v a03 e il integral linearity error ? ? 10.0 lsb ? v ref ? 5.0v a04 e dl differential linearity error ? ? +6.0/-4.0 lsb ? v ref ? 5.0v a06 e off offset error ? ? 25 lsb ? v ref ? 5.0v a07 e gn gain error ? ? 15 lsb ? v ref ? 5.0v a10 ? monotonicity ( 1 ) ?v ss ? v ain ?? v ref a20 ? v ref reference voltage range (v refh ? v refl ) 3?av dd ? av ss v a21 v refh reference voltage high av ss + 3.0v ? av dd + 0.3v v a22 v refl reference voltage low av ss ? 0.3v ? av dd ? 3.0v v a25 v ain analog input voltage v refl ?v refh v note 1: the a/d conversion result never decreases with an increase in the input voltage. a2 a3 a4 xx x
pic18f66k80 ds80519d-page 4 ? 2011 microchip technology inc. 2. module: eusart in synchronous transmit mode, data may be cor- rupted if using the txxif bit to determine when to load the txregx register. one or more of the intended transmit messages may be incorrect. work around a fixed delay added before loading the txregx may not be a reliable work around. when load- ing the txregx, check that the trmt bit inside of the txstax register is set instead of checking the txxif bit. the following code can be used: while(!txstaxbits.trmt); // wait to load txregx until trmt is set affected silicon revisions 3. module: eccp the tri-state setting of the auto-shutdown feature, in the enhanced pwm, will not success- fully drive the pin to tri-state. the pin will remain an output and should not be driven externally. all tri-state settings will be affected. work around use one of the other two auto-shutdown states available, as outlined in the data sheet. affected silicon revisions 4. module: ecan the clksel bit in the ciocon register remains modifiable while the ecan module is not in con- figuration mode. accidental state changes of this bit will result in immediate bit clock changes that will affect all nodes on the bus. work around while the ecan module is in run mode, do not modify the state of the clksel bit in the ciocon register unless the can module is first changed into configuration mode. affected silicon revisions 5. module: ultra low-power sleep entering ultra low-power sleep mode by setting reten = 0 and sreten = 1 , will cause the part to not be programmable through icsp. this issue occurs when the reten fuse bit in config1l<0> is cleared to ? 0 ?, the sreten bit in the wdtcon register is set to ? 1 ? and a sleep instruction is executed within the first 350 ? s of code execution. this happens after a reset event, causing the part to enter ultra low-power sleep mode. work around use normal sleep and low-power sleep modes only, or on any reset, ensure that at least 350 ? s passes before executing a sleep instruction when ulp is enabled. to ensure the ultra low-power sleep mode is not enabled, the reten fuse bit in config1l<0> should be set to a ? 1 ?, and the sreten bit in the wdtcon register should be cleared to a ? 0 ?. the following code can be used: //this will ensure the reten fuse is set to 1 #pragma config reten = off //this will ensure the sreten bit is 0 wdtconbits.sreten = 0; if the ultra low-power sleep mode is needed, then the user must ensure that the minimum time, before the first sleep instruction is executed, is greater than 350 ? s. affected silicon revisions a2 a3 a4 x a2 a3 a4 xx x a2 a3 a4 x a2 a3 a4 x
? 2011 microchip technology inc. ds80519d-page 5 pic18f66k80 6. module: i pd and i dd the i pd and i dd limits do not match the data sheet. the i pd values, shown in bold in section 31.2 ?dc characteristics: power- down and supply current pic18f66k80 family (industrial/extended)? (below), reflect the updated silicon maximum limits. all i dd maximum limits will equal 2.8 times the value listed in the data sheet. affected silicon revisions . a2 a3 a4 x 31.2 dc characteristics: power-down and supply current pic18f66k80 family (industrial/extended) pic18f66k80 (industrial/extended) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device typ max units conditions power-down current (i pd ) (1) pic18lfxxk80 0.008 7 a -40c v dd = 1.8v (4) (sleep mode) regulator disabled 0.013 7 a +25c 0.035 9 a +60c 0.218 10 a +85c 3 12 a 125oc pic18lfxxk80 0.014 8 a -40c v dd = 3.3v (4) (sleep mode) regulator disabled 0.034 8 a +25c 0.092 9 a +60c 0.312 10 a +85c 4 16 a 125oc pic18fxxk80 0.2 9 a -40c v dd = 3.3v (sleep mode) regulator enabled 0.23 9 a +25c 0.32 10 a +60c 0.51 11 a +85c 5 18 a 125oc pic18fxxk80 0.22 10 a -40c v dd = 5v (5) (sleep mode) regulator enabled 0.24 10 a +25c 0.34 11 a +60c 0.54 12 a +85c 5 20 a 125oc legend: shading of rows is to assist in readability of the table. note 1: the power-down current in sleep mode does not depend on t he oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss , and all features that add delta current disabled (such as wdt, sosc oscillator, bor, etc.). 2: the supply current is mainly a function of operating voltage, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code ex ecution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temp erature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. 4: for lf devices, reten (config1l<0>) = 1 . 5: for f devices, sreten (wdtcon<4>) = 1 and reten (config1l<0>) = 0 .
pic18f66k80 ds80519d-page 6 ? 2011 microchip technology inc. 7. module: reset (bor) an unexpected reset may occur if the brown- out reset module (bor) is disabled, and then re-enabled, when the high/low-voltage detection module (hlvd) is not enabled (hlvdcon<4> = 0 ). this issue affects bor modes: boren<1:0> = 10 and boren<1:0> = 01 . in both of these modes, if the bor module is re-enabled while the device is active, unexpected resets may be generated. work around if bor is required and power consumption is not an issue, use boren<1:0> = 11 . for boren<1:0> = 10 mode, either switch to boren<1:0> = 11 mode or enable the hlvd (hlvdcon<4> = 1 ) prior to entering sleep. if power consumption is an issue and low power is desired, do not use boren<1:0> = 10 mode. instead, use boren<1:0> = 01 and follow the steps below when entering and exiting sleep. 1. disable bor by clearing sboren (rcon<6> = 0 ). wdtconbits.sboren = 0; 2. enter sleep mode (if desired). sleep(); 3. after exiting sleep mode (if entered), enable the hlvd bit (hlvdcon<4> = 1 ). hlvdconbits.hlvden = 1; 4. wait for the internal reference voltage (t irvst ) to stabilize (typically 25 ? s). while(!hlvdconbits.irvst); 5. re-enable bor by setting sboren (rcon<6> = 1 ). wdtconbits.sboren = 1; 6. disable the hlvd by clearing hlvden (hlvdcon<4> = 0 ). hlvdconbits.hlvden = 0; affected silicon revisions 8. module: ecan the enhanced window address feature, ewin<4:0>, in the ecancon register, will not move the bncon 0< n< 5 registers into the access window of ram. the rest of the registers in b0 through b5 will be transferred into the access bank successfully. this feature is only available in mode 1 and mode 2; mode 0 applications will not be affected. work around 1. set the ecancon register ewin bits to the desired buffer. ecanconbits.ewin = buffer_selection; 2. decode the desired buffer to each individual buffer control register, bncon 0< n< 5. switch( buffer_selection ) { //ewin code for buffer b0 case 18: break; //ewin code for buffer b5 case 23: break; default: break; } 3. process information in the selected buffer control register. note that the bncon 0< n< 5 control registers can be set up for either transmit or receive operations. case 18: //save b0con and clear flags being processed temp = b0con; //clear any flags break; 4. continue processing the rest of the buffer in the windowed location. affected silicon revisions a2 a3 a4 xx x a2 a3 a4 x
? 2011 microchip technology inc. ds80519d-page 7 pic18f66k80 9. module: mclre the master clear pin will not be readable when mclre is set to off for all 28-pin part variants (pic18f2xk80). when the mclre bit, config3h<7>, is cleared on 28-pin devices, the mclr pin will be disabled but input data will not be available on re3. work around none. affected silicon revisions 10. module: timer1/timer3 timer1 and timer3 gate control will not function up to the speed of f osc when the txcon is set to the system clock (txcon<7:6> = 01 ). results will always be at the resolution of f osc /4, although the internal f osc has been selected as the clock source. work around use the external clock input pin setting, txcon<7:6> = 10 and txcon<3> = 0 . affected silicon revisions a2 a3 a4 xx x a2 a3 a4 xx
pic18f66k80 ds80519d-page 8 ? 2011 microchip technology inc. data sheet clarifications the following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (ds39977 d ): 1. module: rxfcon registers table 6-1 on page 116 of the data sheet should show the following register addresses: e47h-rxfcon1 e46h-rxfcon0 2. module: rxfcon registers table 6-2 on page 125 of the data sheet should show the following register addresses: e47h-rxfcon1 e46h-rxfcon0 3. module: listen only mode page 441, section 27.3.4 ?listen only mode? will be revised to: listen only mode provides a means for the pic18f66k80 family devices to receive all mes- sages, including messages with errors. this mode can be used for bus monitor applications or for detecting the baud rate in ?hot plugging? situations. for auto-baud detection, it is neces- sary that there are at least two other nodes which are communicating with each other. the baud rate can be detected empirically by testing different values until valid messages are received. the listen only mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or acknowledge signals. in listen only mode, both valid and invalid messages will be received regardless of rxmn bit settings. the filters and masks can still be used to allow only particular valid messages to be loaded into the receive registers, or the filter masks can be set to all zeros to allow a mes- sage with any identifier to pass. all invalid messages will be received in this mode, regardless of filters and masks or rxmn receive buffer mode bits. the error counters are reset and deactivated in this state. the listen only mode is activated by setting the mode request bits in the cancon register. note: corrections are shown in bold . where possible, the original bold text formatting has been removed for clarity.
? 2011 microchip technology inc. ds80519d-page 9 pic18f66k80 4. module: a/d converter characteristics the values in table 31-25 reflect the updated a/d converter characteristics. the new information is shown in bold text. table 31-25: a/d converter characteristics: pic18f66k80 (industrial/extended) 5. module: hlvd note 1 under register 26-1: hlvdcon, on page 387, should direct to parameter d420: note 1: for the electrical specifications, see parameter d420 in section 31.0 ?electrical characteristics?. 6. module: power-up timer period table 31-11 on page 572 of the data sheet, parameter 33 t pwrt will be revised to a typical value of 1.0 ms . param no. sym characteristic min typ max units conditions a01 n r resolution ? ? 12 bit ? v ref ? 5.0v a03 e il integral linearity error ? <1 6.0 lsb ? v ref ?? 5.0v a04 e dl differential linearity error ? <1 +3.0/-1.0 lsb ? v ref ?? 5.0v a06 e off offset error ? <1 9.0 lsb ? v ref ?? 5.0v a07 e gn gain error ? <1 8.0 lsb ? v ref ?? 5.0v a10 ? monotonicity ( 1 ) ? ?v ss ? v ain ? v ref a20 ? v ref reference voltage range (v refh ? v refl ) 3?v dd ? v ss v for 12-bit resolution a21 v refh reference voltage high av ss + 3.0v ? av dd + 0.3v v for 12-bit resolution a22 v refl reference voltage low av ss ? 0.3v ? av dd ? 3.0v v for 12-bit resolution a25 v ain analog input voltage v refl ?v refh v a28 av dd analog supply voltage v dd ? 0.3 ? v dd + 0.3 v a29 av ss analog supply voltage v ss ? 0.3 ? v ss + 0.3 v a30 z ain recommended impedance of analog voltage source ??2.5k ? a50 i ref v ref input current (2) ? ? ? ? 5 150 ? a ? a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never decreases with an increase in the input voltage. 2: v refh current is from the ra3/an3/v ref + pin or v dd , whichever is selected as the v refh source. v refl current is from the ra2/an2/v ref -/cv ref pin or v ss , whichever is selected as the v refl source.
pic18f66k80 ds80519d-page 10 ? 2011 microchip technology inc. appendix a: document revision history rev a document ( 2/ 201 1) initial release of this document; issued for revision, a2. includes silicon issues 1 (analog-to-digital con- verter), 2 (eusart), 3 (eccp), 4 (ecan), 5 (ultra low-power sleep) and 6 (i pd and i dd ). rev b document (4/2011) added silicon issues 7 (reset ? bor) and 8 (ecan). added data sheet clarifications 1, 2 (rxfcon registers) and 3 (listen only mode). rev c document ( 9/ 2011) added table 3 , 10-bit a/d converter characteristics to silicon issue 1 (analog-to-digital converter). added silicon issues 9 (mclre) and 10 (timer1/timer3). added data sheet clarifications 4 (a/d converter characteristics) and 5 (hlvd). rev d document (12/2011) added silicon revision a4; includes issues 1 (analog- to-digital converter ? a/d), 3 (eccp), 7 (reset ? bor) issues 9 (mclre). added data sheet clarification 6 (power-up timer period). updated data sheet revision level to ?d?. all previous clarifications carried into this revision.
? 2011 microchip technology inc. ds80519d-page 11 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2011, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-61341-879-6 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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